开关电容电路概述

开关电容(SC)电路是由受时钟信号控制的开关和电容器组成的电路。它是利用电荷的存储和转移来实现对信号的各种处理功能。在实际电路中，有时仅用开关和电容器构成的电路往往不满足要求，所以多与放大器或运算放大器、比较器等组合起来，以实现电信号的产生、变换与处理。

利用开关电容电路来处理模拟信号在1972年首先提出，由于它具有的一些特殊的优点，引起了人们的重视，并加强了这方面的研究工作。1977年发表了采用NMOS工艺和开关电容技术构成的环路滤波器，1978年美国Intel公司首先制成用于PCM电话系统的话路滤波器，从而进入了实用阶段。近年来，对开关电容的理论、分析方法和电路技术进行了多方面的研究，进一步拓展了开关电容电路技术在模拟信号处理领域的应用范围。

由于开关电容电路使用MOS工艺，尺寸小，功耗低，工艺过程比较简单，易于大规模集成，因此得到了较快的发展和广泛的应用。2100433B

目录

Preface

Acknowledgment

ListofAbbreviations

ListofFigures

ListofTables

1INTRODUCTION

1.High-FrequencyIntegratedAnalogFiltering

2.MultirateSwitched-CapacitorCircuitTechniques

3.Sampled-DataInterpolationTechniques

4.ResearchGoalsandDesignChallenges

2IMPROVEDMULTIRATEPOLYPHASE-BASEDINTERPOLATIONSTRUCTURES

1.Introduction

2.ConventionalandImprovedAnalogInterpolation

3.PolyphaseStructuresforOptimum-classImprovedAnalogInterpolation

4.MultirateADBPolyphaseStructures

4.1CanonicandNon-CanonicADBRealizations

4.2SCCircuitArchitectures

5.Low-SensitivityMultirateIIRStructures

5.1MixedCascade/ParallelForm

5.2Extra-RippleIIRForm

6.Summary

3PRACTICALMULTIRATESCCIRCUITDESIGNCONSIDERATIONS

1.Introduction

2.PowerConsumptionAnalysis

3.Capacitor-RatioSensitivityAnalysis

3.1FIRStructure

3.2IIRStructure

4.FiniteGain&BandwidthEffects

5.Input-ReferredOffsetEffects

6.PhaseTiming-MismatchEffects

6.1PeriodicFixedTiming-SkewEffect

6.2RandomTiming-JitterEffects

7.NoiseAnalysis

8.Summary

4GAIN-ANDOFFSET-COMPENSATIONFORMULTIRATESCCIRCUITS

1.Introduction

2.AutozeroingandCorrelated-DoubleSamplingTechniques

3.AZandCDSSCDelayBlockswithMismatch-FreeProperty

3.1SCDelayBlockArchitectures

3.2GainandOffsetErrors-ExpressionsandSimulationVerification

3.3Multi-UnitDelayImplementations

4.AZandCDSSCAccumulators

4.1SCAccumulatorArchitectures

4.2GainandOffsetErrors-ExpressionsandSimulationVerification

5.DesignExamples

6.SpeedandPowerConsiderations

7.Summary

5DESIGNOFA108MHzMULTISTAGESCVIDEOINTERPOLATINGFILTER

1.Introduction

2.OptimumArchitectureDesign

2.1MultistagePolyphaseStructurewithHalf-BandFiltering..

2.2Spread-ReductionScheme

2.3Coefficient-SharingTechniques

3.CircuitDesign

3.1lst-Stage

3.22nd-and3rd-Stage

3.3DigitalClockPhaseGeneration

4.CircuitLayout

5.SimulationResults

5.1BehavioraISimulations

5.2Circuit-LevelSimulations

6.Summary

6DESIGNOFA320MHZFREQUENCY-TRANSLATEDSCBANDPASSINTERPOLATINGFILTER

1.Introduction

2.PrototypeSystem-LevelDesign

2.1Multi-notchFIRTransferFunction

2.2Time-InterleavedSerialADBPolyphaseStructurewith

Autozeroing

3.PrototypeCircuit-LevelDesign

3.1AutozeroingADBandAccumulator

3.2High-SpeedMultiplexer

3.3OverallSCCircuitArchitecture

3.4TelescopicopampwithWide-SwingBiasing

3.5nMOSSwitches136

3.6NoiseCalculation

3.7I/0Circuitry

3.8LowTiming-SkewClockGeneration

4.LayoutConsiderations

4.1DeviceandPathMatching

4.2SubstrateandSupplyNoiseDecoupling

4.3Shielding

4.4FloorPlan

5.SimulationResults

5.1OpampSimulations

5.2FilterBehavioralSimulations

5.3FilterTransistor-LevelandPost-LayoutSimulations

6.Summary

7EXPERIMENTALRESULTS

1.Introduction

2.PCBDesign

2.1FloorPlan

2.2PowerSuppliesandDecoupling

2.3BiasingCurrents

2.4InputandOutputNetwork

3.MeasurementSetupandResults

3.1FrequencyResponse

3.2Time-DomainSignalWaveforms

3.3One-ToneSignalSpectrum

3.4Two-ToneIntermodulationDistortion

3.5THDandIM3vs.InputSignalLevel

3.6NoisePerformance

3.7CMRRandPSRR

4.Summary

8CONCLUSIONS

APPENDIX1TIMING-MISMATCHERRORSWITHNONUNIFORMLYHOLDINGEFFECTS

1.SpectrumExpressionsforIU-ON(SH)andIN-CON(SH)

1.1IU-ON(SH)

1.2IN-CON(SH)

2.ClosedFormSINADExpressionforIU-ON(SH)andIN-CON(SH)

2.1IU-ON(SH)

2.2IN-CON(SH)

3.ClosedFormSFDRExpressionforIN-CON(SH)systems

4.SpectrumCorrelationofIN-OU(IS)andIU-ON(SH)

APPENDIX2NOISEANALYSISFORSCADBDELAYLINEANDPOLYPHASESUBFILTERS

1.OutputNoiseofADBDelayLine

2.OutputNoiseofPolyphaseSubfilters

2.1UsingTSIInputCoefficientSCBranches

2.2UsingOFRInputCoefficientSCBranches

APPENDIX3GAIN,PHASEANDOFFSETERRORSFORGOCMFSCDELAYCIRCUITIANDJ

1.GOCMFSCDelayCircuitI

2.GOCMFSCDelayCircuitJ2100433B